1. Field of the Invention
The apparatus and method of present invention relates generally to memory systems, and more particularly relates to a multi-port memory cell having reduced transistor count and a method of accessing row addresses in a multi-port memory array.
2. Description of the Prior Art
Multi-port dynamic random access memory (DRAM) is well known in the prior art, as is volatile static random access memory (SRAM). DRAM has a distinct advantage of utilizing a fewer number of transistors than its SRAM counterpart, thereby enabling much higher memory densities to be fabricated on a single integrated circuit (IC) chip. A disadvantage of using DRAM has been its relatively slow access time, primarily due to a relative large wordline capacitance typically employed to store the logic state of the memory cell in a large DRAM array. It is also required in DRAM that data be restored after read operation and regularly refreshed. Moreover, once power is removed from the DRAM, all data is lost or otherwise invalid. Therefore, for certain applications, such as for cache architectures which often require high speed memory access, SRAM has found considerable advantage in that it has the ability to latch its data without refreshing the data. SRAM also can provide a much faster access time for writing to memory, as compared to conventional DRAM. Furthermore, since data stored in memory cells are not destroyed after read operation, memory access operation in SRAM does not require data write-back operation.
However, the cost for the added benefits of SRAM is that the number of transistors used to fabricate a memory cell is considerably higher than its DRAM counterpart. Consequently, the storage density for SRAM is considerably lower than for DRAM, thereby making the cost per byte of storage significantly higher for SRAM than it is for DRAM, even considering that the additional memory refresh timing requirements and associated circuitry for DRAM are more complex.
As an example of a typical multi-port DRAM configuration, consider U.S. Pat. No. 5,923,593 to Hsu et al. Hsu et al. disclose a four-port DRAM structure having four transistors, with each transistor connected to a common capacitor for storing the logical state of the memory cell. As is typically the case in conventional DRAM configurations, however, in order for the data stored in the DRAM cell to remain valid, the data must be periodically refreshed. Moreover, when power is removed from the DRAM, all data is lost.
An example of a four-port SRAM is disclosed in U.S. Pat. No. 5,260,908 to Ueno. Ueno discloses a four-port SRAM array which does not require periodical data refresh. However, each memory cell in the four-port SRAM array requires sixteen transistors, instead of four transistors plus a capacitor in case of four-port DRAM memory cell, thus it has relatively large size of memory array.
There remains a need, therefore, in the field of multi-port memory, for a multi-port memory cell that does not require refreshing, and the circuitry associated therewith, and is fabricated with a minimal number of circuit components, thereby providing cost effective high density memory storage capability on a single integrated circuit chip.
It is an object of the present invention to provide a memory array having multiple ports which are accessible by multiple wordlines simultaneously. The memory array includes multiple memory cells each of which has multiple ports associated with the multiple wordlines.
It is another object of the present invention to provide a multi-port memory cell that is fabricated using a minimum number of circuit components and utilizing a cross-shape memory cell layout to improve the overall packing density of the memory array.
It is yet another object of the present invention to provide a multi-port, two-way memory array that can be simultaneously accessed with multi-port capability in the row (horizontal) direction or the column (vertical) direction.
It is a further object of the present invention to provide a method for accessing a multi-port memory array without suffering data contention problems.
The present invention revolutionizes multi-port memory design by providing a memory device or cell including a single transistor for each port, each of the transistors sharing a common floating gate. In a preferred embodiment of the present invention, a multi-port memory cell is provided which comprises a plurality of ports through which the wordlines and bit-lines are provided, a plurality of transistor devices each of which corresponds to each of the plurality of ports, is coupled to a wordline and a bit-line through a corresponding port and gated by a wordline, and also has a conduction path of which a first end is connected to a bit-line, and a charge storage device commonly connected to a second end of a conduction path of each of the plurality of transistor devices, where the charge storage device is charged when any of the plurality of transistor devices is activated.
Each of the transistor devices preferably has a gate terminal coupled to a wordline and a drain terminal coupled to a bit-line. Source terminals of the transistor devices are operatively connected together and form a source line, and the source line is connected to the charge storage device.
The above-described memory cells may constitute a memory array which has multiple ports each of which is associated with a corresponding port of each of the memory cells, where a group of memory cells are accessed by a group of wordlines through corresponding one of the multiple ports of the memory array. The memory cells may be divided into at least four groups including a first group of memory cells accessed by a first group of wordlines through a first group of ports, a second group of memory cells accessed by a second group of wordlines through a second group of ports, a third group of memory cells accessed by a third group of wordlines through a third group of ports, and a fourth group of memory cells accessed by a fourth group of wordlines through a fourth group of ports. The first through fourth groups of wordlines simultaneously access the first through fourth groups of memory cells, respectively.
In accordance with another form of the present invention, a two-port, two-way memory array is provided which includes multiple two-port, two-way memory cells which are simultaneously accessed by one of first and second sets of wordlines, wherein the wordlines are divided into the first set of wordlines arranged in the row direction and the second set of wordlines arranged in the column direction.
The present invention also provides a system for addressing a memory array having multiple ports through which request command signals and row address signals are provided. The system preferably comprises a conflict detector for detecting a conflict between two or more of the row address signals to generate a conflict control signal corresponding to the conflict detected, a priority logic circuit for performing a logic operation with respect to the request command signals based on a predetermined priority logic to generate prioritized signals, and a selection unit for selecting one of a request command signal and a prioritized signal corresponding to the request command signal in response to the conflict control signal, wherein a signal selected by the selection unit selects a corresponding one of the row address signals.
The conflict detector preferably includes a comparison unit for comparing the row address signals to generate conflict signals each of which represents a conflict between two of the row address signals, and a logic operation unit for performing a predetermined logic operation with respect to the conflict signals to generate the conflict control signal representing a conflict between a certain row address signal and at least one of other row address signals.
The priority logic circuit preferably includes a plurality of inputs each of which receives one of the request command signals through corresponding one of the multiple ports, and a plurality of outputs each of which generates one of the prioritized signals to the selection unit, each of the prioritized signals corresponding to each of the request command signals.
The selection unit preferably includes a plurality of selectors each of which has a first input receiving a request command signal, a second input connected to corresponding one of the plurality of outputs of the priority logic circuit to receive a prioritized signal corresponding to the request command signal, and a third input receiving a conflict control signal from the conflict detector, wherein a selector selects one of the request command signal and the prioritized signal in response to the conflict control signal.
These and other objects, features and advantages of the present invention will become apparent from the following detailed description of the preferred embodiments thereof, which is to be read in conjunction with the accompanying drawings, wherein like elements are designated by identical reference numerals throughout the several views.